A differential built-in current sensor design for high speed IDDQ testing

Author

Hurst, Jason P. ; Singh, Adit D.

Author_Institution

Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA

fYear

1995

fDate

4-7 Jan 1995

Firstpage

419

Lastpage

423

Abstract

A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated through MOSIS 2.0-micron n-well technology. At clock speeds of up to 31.65 MHz the sensor accurately detects all six of the defects that were implanted in the test chip

Keywords

CMOS digital integrated circuits; VLSI; built-in self test; design for testability; electric current measurement; electric sensing devices; integrated circuit design; integrated circuit testing; 2 micron; 31.25 MHz; BIST environment; MOSIS; built-in current sensor design; built-in self-test; differential architecture; high speed IDDQ testing; n-well technology; quiescent current detection; Built-in self-test; Circuit faults; Circuit testing; Clocks; Electrical fault detection; Fault detection; Integrated circuit testing; Latches; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1995., Proceedings of the 8th International Conference on

Conference_Location

New Delhi

ISSN

1063-9667

Print_ISBN

0-8186-6905-5

Type

conf

DOI

10.1109/ICVD.1995.512150

Filename

512150