Hybrid lattice reduction algorithm and its implementation on an SDR baseband processor for LTE

Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. This paper proposes a Hybrid LR algorithm (HLR), which is a scalable LR algorithm. HLR is specifically designed and optimised to exploit ILP and DLP features offered by parallel programmable baseband architectures. Abundant vector-parallelism in HLR is enabled with highly-regular and deterministic data-flow. Hence, HLR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) baseband architectures. HLR can be adapted to operate in two different modes to achieve the best performance/cycle trade-off, which is highly desirable for SDR baseband processing. The proposed algorithm has been evaluated in the context of 3GPP-LTE and implemented on ADRES which is a Coarse Grain Reconfigurable Array (CGRA) processor. Most of the previously reported implementations of LR algorithms are for ASIC or FPGA. However, to the best of author´s knowledge, this is the first reported LR algorithm explicitly designed and optimized, to have a scalable and adaptive implementation for a CGRA processor like ADRES. The reported implementation of HLR can achieve gains of up to 12 dB compared to ZF for MIMO detection.