A programmable power-efficient decimation filter for software radios

Author

Farag, Emad N. ; Yan, Ran-Hong ; Elmasry, Mohamed I.

Author_Institution

VLSI Res. Group, Waterloo Univ., Ont., Canada

fYear

1997

fDate

18-20 Aug. 1997

Firstpage

68

Lastpage

71

Abstract

Several high-level low-power design techniques have been incorporated in the design of a decimation filter for software radio. These include; operation minimization, multiplier elimination and block deactivation. Analysis and simulation results indicate that these techniques can achieve a 4 times reduction in power dissipation. An interleaved multiplier-accumulator array is used in the lowpass filter. The decimation filter designed has a programmable resolution, that varies from 12 to 20 bits. The entire decimation filter has been designed in a 3.3 Volt 0.5 /spl mu/m CMOS technology.

Keywords

CMOS digital integrated circuits; VLSI; digital filters; digital radio; low-pass filters; programmable filters; radio receivers; 0.5 micron; 12 to 20 bit; 3.3 V; CMOS technology; block deactivation; high-level low-power design techniques; interleaved multiplier-accumulator array; lowpass filter; multiplier elimination; operation minimization; power dissipation reduction; power-efficient decimation filter; programmable power-efficient decimation filter; Analog-digital conversion; Band pass filters; CMOS technology; Delta-sigma modulation; Dynamic range; Hardware; Permission; Power dissipation; Signal resolution; Software radio;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-89791-903-3

Type

conf

Filename

621241