Next generation radiation-hardened SRAM for space applications

Author

Hafer, Craig ; Mabra, Jonathan ; Slocum, Duane ; Kalkur, T.S.

Author_Institution

Aeroflex Colorado Springs, CO

fYear

0

fDate

0-0 0

Abstract

Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC´s 0.18mum shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset (SEU) due to charged particle strikes are mitigated by a combination of circuit design techniques, error detection and correction (EDAC), and enhanced layout design rules. The 16M-bit SRAM is SEL immune to greater than 105 MeV-cm²/mg. The SEU error rate is less than 2.9times10^-16 errors/bit-day

Keywords

CMOS integrated circuits; SRAM chips; embedded systems; error correction; error detection; integrated circuit design; isolation technology; radiation effects; 0.18 micron; CMOS; circuit design; error correction; error detection; ionizing dose; layout design; monolithic SRAM; radiation-hardened SRAM; shallow trench isolation; single event latchup; single event upset; CMOS process; Circuit synthesis; Error analysis; Error correction; Event detection; Ionizing radiation; Minimally invasive surgery; Random access memory; Single event upset; Springs;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference, 2006 IEEE

Conference_Location

Big Sky, MT

Print_ISBN

0-7803-9545-X

Type

conf

DOI

10.1109/AERO.2006.1655956

Filename

1655956