Title :
SEU mitigation for reconfigurable FPGAs
Author :
Czajkowski, David R. ; Samudrala, Praveen K. ; Pagey, Manish P.
Abstract :
This paper, discusses the application of Space Micro´s Time-Triple Modular Redundancy (TTMRtrade) and Hardened-Core (H-Coretrade) technologies (Czajkowski et al., 2005) for Xilinx Virtex-II FPGAs. TTMR is the application of time and spatial redundancy for mitigating single event upsets (SEU). H-Core is an auxiliary rad-hard chip used for mitigating single event functional interrupts (SEFI). These technologies have been proven to perform excellently under radiation and are presently the driving force behind our powerful rad-hard computers built from COTS processors (Czajkowski et al., 2003). These same technologies with a few modifications have been applied to mitigate SEUs, configuration upsets and SEFIs in Virtex-II FPGAs. The application of TTMR and H-Core2 has been successfully demonstrated to mitigate SEUs and SEFIs under radiation. The target system has been named as signal processing node (SPN). SPN is an ideal system for obtaining high performance rad-hard system at a low cost. SPN has the potential of outperforming a similar system built from expensive rad-hard electronics (from rad-hard processes)
Keywords :
field programmable gate arrays; radiation effects; reconfigurable architectures; COTS processors; Xilinx Virtex-II FPGA; hardened-core technology; rad-hard chip; rad-hard computers; radiation; reconfigurable FPGA; signal processing node; single event functional interrupts; single event upsets; time-triple modular redundancy; Circuits; Costs; Field programmable gate arrays; Mission critical systems; Radiation effects; Radiation hardening; Random access memory; Redundancy; Single event upset; Space technology; FPGA; H-Core; SEFI; SEU; TMR; TTMR; XILINX; radiation;
Conference_Titel :
Aerospace Conference, 2006 IEEE
Conference_Location :
Big Sky, MT
Print_ISBN :
0-7803-9545-X
DOI :
10.1109/AERO.2006.1655957
