Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors

Recent IBM processors used in various computer systems including gaming systems are a very aggressive design, addressing three main challenges of the processor design -Memory wall, Power wall and ILP wall. To break these walls the some designs utilized multi threaded, multi core and yet high frequency. These kinds of designs increased the complexity of the test stream generation for processor verification especially in a stress test environment. Moreover Cell Broadband Engine ^TM (Cell/B.E.) utilizes heterogeneous multi core, multi threaded with high. This further increased the complexity of the verification. This paper describes some of the scenarios, the Post Silicon Verification team addressed in their effort of verification of the Cell/B.E. and other game processors.