DocumentCode
227103
Title
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution
Author
Cassidy, Andrew S. ; Alvarez-Icaza, Rodrigo ; Akopyan, Filipp ; Sawada, Jun ; Arthur, John V. ; Merolla, Paul A. ; Datta, Piyali ; Gonzalez Tallada, Marc ; Taba, Brian ; Andreopoulos, Alexander ; Amir, Arnon ; Esser, Steven K. ; Kusnitz, Jeff ; Appuswamy,
fYear
2014
fDate
16-21 Nov. 2014
Firstpage
27
Lastpage
38
Abstract
Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highly optimized software expression of the kernel, here, we demonstrate True North, a co-designed silicon expression of the kernel. True North achieves five orders of magnitude reduction in energy to-solution and two orders of magnitude speedup in time-to solution, when running computer vision applications and complex recurrent neural network simulations. Breaking path with the von Neumann architecture, True North is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt. We demonstrate seamless tiling of True North chips into arrays, forming a foundation for cortex-like scalability. True North´s unprecedented time-to-solution, energy-to-solution, size, scalability, and performance combined with the underlying flexibility of the kernel enable a broad range of cognitive applications.
Keywords
computer vision; neural chips; neural net architecture; recurrent neural nets; True North chips; codesigned silicon expression; complex recurrent neural network simulation; computer vision application; cortex-like scalability; energy to-solution; energy-to-solution; giga-synaptic OPS/Watt; magnitude reduction; magnitude speedup; neuroscience; neurosynaptic computation; parallel event-driven kernel; real-time scalable cortical computing; software expression; synapse brain-inspired neurosynaptic processor; time-to-solution; von Neumann architecture; Compass; Computational modeling; Computer architecture; Kernel; Message systems; Nerve fibers;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing, Networking, Storage and Analysis, SC14: International Conference for
Conference_Location
New Orleans, LA
Print_ISBN
978-1-4799-5499-5
Type
conf
DOI
10.1109/SC.2014.8
Filename
7012190
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