A 10-bit 200-MS/s reconfigurable pipelined A/D converter

A reconfigurable pipelined analog-to-digital converter (ADC) has been fabricated in a 90-nm CMOS technology. The analysis and design of the reconfigurable architecture are presented. Based on various system performance requirements, the suitable configuration can be adopted. The proposed ADC is designed for all the configurations under different bandwidth requirements to prove that the reconfiguration will save significant power consumption. Simulated output codes of the designed ADC exhibit a SNDR of 59.0 dB at 200 MHz while the measurement SNDR is 48.6 dB at 160-MS/s sampling rate. The active area of the design is 0.27 mm², and the power consumption at full speed is 26mW from a 1V supply voltage.