DocumentCode
2271680
Title
The Complexity of Fault-Tolerant Adder Structures
Author
Biernat, Janusz
Author_Institution
Inst. of Comput. Eng., Wroclaw Univ. of Technol., Warsaw
fYear
2008
fDate
26-28 June 2008
Firstpage
316
Lastpage
323
Abstract
To achieve fault-tolerance property of arithmetic circuits several approaches are possible, that differ in the level of hardware redundancy and the coverage of detectable faults. Among them only two are applicable to design of fast fault-tolerant adders. They exploit the concept of residue code or double-rail code. The complexity comparison of the respective fast fault-tolerant adders will be presented.
Keywords
adders; fault tolerance; redundancy; residue codes; arithmetic circuits; double-rail code; fault-tolerant adder; hardware redundancy; residue code; Adders; Arithmetic; Circuit faults; Control engineering computing; Electrical fault detection; Equations; Fault tolerance; Fault tolerant systems; Hardware; Logic; arithmetic devices; fast adder; fault-tolerant adder;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependability of Computer Systems, 2008. DepCos-RELCOMEX '08. Third International Conference on
Conference_Location
Szklarska Poreba
Print_ISBN
978-0-7695-3179-3
Type
conf
DOI
10.1109/DepCoS-RELCOMEX.2008.60
Filename
4573072
Link To Document