Organization of AES Cryptographic Unit for Low Cost FPGA Implementation

This paper discusses different design options for realization of AES cryptographic algorithm in programmable logic devices and illustrates them with practical results of hardware implementation. The discussion begins with those aspects of the four basic cipher transformations that are essential for realization with resources available in FPGA devices, then moves to various possible organizations of the cipher unit and concludes with efficiency and size comparison of results obtained after implementation of the AES-128 version of the method in Spartan-3 devices from Xilinx. Instead of searching for a "global optimum" specific low-cost FPGA implementation, the paper summarizes main directions of design development that are viable today and evaluates them by a case study example.