DocumentCode :
2271811
Title :
Port assignment for interconnect reduction in high-level synthesis
Author :
Cong, Hao ; Chen, Song ; Yoshimura, Takeshi
Author_Institution :
Grad. Sch. of IPS, Waseda Univ., Kitakyushu, Japan
fYear :
2012
fDate :
23-25 April 2012
Firstpage :
1
Lastpage :
4
Abstract :
This paper focuses on the Port Assignment Problem for Binary Commutative Operators (PAP-BCO) in high-level synthesis. Given a binding of operations and variables, the PAP-BCO pursues to build the connections of registers to functional units with an objective of minimizing the number of interconnections. In this paper, we formulate the PAP-BCO as a vertex partitioning problem on a graph, and propose an exact Integer Linear Programming (ILP) based method and a fast iterative method based on elementary transformations of spanning tree to solve it. Experimental results show that the fast iterative algorithm can get the optimum solutions in 97% runs. At the same time, the running time is only tens of milliseconds for the maximum test case with 64 registers and 140 operations, on which the ILP based method ran out of time.
Keywords :
high level synthesis; integer programming; integrated circuit interconnections; iterative methods; linear programming; trees (mathematics); binary commutative operators; elementary transformations; fast iterative method; high-level synthesis; integer linear programming; interconnect reduction; port assignment problem; spanning tree; vertex partitioning problem; Algorithm design and analysis; Integrated circuit interconnections; Multiplexing; Partitioning algorithms; Registers; Resource management; Vegetation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
ISSN :
PENDING
Print_ISBN :
978-1-4577-2080-2
Type :
conf
DOI :
10.1109/VLSI-DAT.2012.6212613
Filename :
6212613
Link To Document :
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