Title :
Automatic synthesis of extended burst-mode circuits using generalized C-elements
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
Presents a new automatic synthesis technique for extended burst-mode circuits, a class of asynchronous circuits that allows multiple input changes between state transitions and a choice of next states based on input signal levels. The target implementation is a pseudo-static asymmetric CMOS complex gate for each output, known as a generalized C-element. The synthesis algorithm generates hazard-free covers for the set and reset functions of each output using Nowick and Dill´s (1995) exact hazard-free logic minimization algorithm. Each output circuit is formed by mapping its set and reset logic to N and P stacks of an asymmetric CMOS gate connected to a sustainer; long-series stacks are decomposed into static gates followed by short stacks. A simple heuristic is used to ensure that no short-circuit paths exist from Vdd to ground. The resulting circuits for small- to medium-size extended burst-mode specifications are 40% smaller and 30% faster than the two-level circuits generated by a 3D synthesis tool, and significantly smaller and faster than the complex-gate circuits generated by the method of Kudva et al. (1996)
Keywords :
CMOS digital integrated circuits; asynchronous circuits; circuit CAD; hazards and race conditions; logic gates; asynchronous circuits; automatic synthesis technique; circuit specifications; exact hazard-free logic minimization algorithm; extended burst-mode circuits; generalized C-elements; hazard-free covers; input signal levels; long-series stacks; multiple input changes; next states; output circuit; pseudo-static asymmetric CMOS complex gate; reset function; set function; short stacks; short-circuit paths; state transitions; static gates; sustainer; Asynchronous circuits; CMOS logic circuits; Circuit synthesis; Clocks; Drives; Energy management; Hazards; Microprocessors; Power dissipation; Signal synthesis;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558219