• DocumentCode
    2272034
  • Title

    A fault-tolerant PE array based matrix multiplier design

  • Author

    Jan, B.-Y. ; Huang, J.-L.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2012
  • fDate
    23-25 April 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Matrix multiplication comprises a significant portion of computation efforts in many engineering and scientific applications. Realizing matrix multiplication in a two-dimensional PE (processing element) array improves computation efficiency; however, reliability and yield issues arise as the PE array complexity grows. This paper presents three fault tolerant schemes for the Cannon algorithm based two-dimensional PE array matrix multiplier. In the twisted column scheme, free PEs take over the tasks of adjacent faulty PEs; this preserves the computation efficiency. The column replacement scheme reallocates the task of a faulty column to a fault-free one; this degrades the overall performance but significantly enhances fault tolerance. The hybrid approach combines the previous two schemes; it achieves the best fault tolerance and incurs no performance degradation if the number of fault PEs is small. Simulation results and overhead analyses are presented to validate the proposed schemes.
  • Keywords
    circuit complexity; fault tolerance; integrated circuit design; integrated circuit reliability; integrated circuit yield; matrix multiplication; Cannon algorithm; PE array complexity; column replacement scheme; computation efficiency; engineering application; fault tolerant scheme; fault-tolerant PE array based matrix multiplier design; faulty column; matrix multiplication; processing element array; reliability; scientific application; twisted column scheme; two-dimensional PE array matrix multiplier; yield; Algorithm design and analysis; Arrays; Degradation; Fault tolerance; Fault tolerant systems; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    PENDING
  • Print_ISBN
    978-1-4577-2080-2
  • Type

    conf

  • DOI
    10.1109/VLSI-DAT.2012.6212624
  • Filename
    6212624