Physical design CAD in deep sub-micron era

We investigate the impacts of miniaturization of device dimensions that causes a paradigm shift in LSI design methodology. Major design issues in deep sub micron LSIs, namely, wire delay, circuit complexity and power consumption are discussed based on scaling theory. To resolve these issues, a concept called layout driven synthesis and optimization Is introduced. Based on this concept, EDA programs including circuit optimizer, clock tree synthesis, technology mappers and so on, have been developed. Timing optimization and power minimization methods using the concept are discussed in detail. Evaluation results obtained by proposed approach show superior performance and dramatic reduction of design period, and indicate validity of layout driven synthesis and optimization concept