DocumentCode :
2272203
Title :
Module assignment for low power
Author :
Chang, Jui-Ming ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1996
fDate :
16-20 Sep 1996
Firstpage :
376
Lastpage :
381
Abstract :
We investigate the problem of minimizing the total power consumption during the binding of operations to functional units in a scheduled data path with functional pipelining and conditional branching for data intensive applications. We first present a technique to estimate the power consumption in a functionally pipelined data path and then formulate the power optimization problem as a max cost multi commodity flow problem and solve it optimally. Our proposed method can augment most high level synthesis algorithms as a post processing step for reducing power after the optimizations for area or speed have been completed. An average power savings of 28% has been observed after we apply our method to pipelined designs that have been optimized using conventional techniques
Keywords :
high level synthesis; logic CAD; optimisation; pipeline processing; power consumption; processor scheduling; average power savings; conditional branching; data intensive applications; functional pipelining; functional units; functionally pipelined data path; high level synthesis algorithms; max cost multi commodity flow problem; module assignment; pipelined designs; post processing step; power consumption; power optimization problem; scheduled data path; total power consumption minimisation; Circuits; Costs; Delay; Design optimization; Energy consumption; Flow graphs; Hardware; Pipeline processing; Power dissipation; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
Type :
conf
DOI :
10.1109/EURDAC.1996.558232
Filename :
558232
Link To Document :
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