Title :
High speed DDR2/3 PHY and dual CPU core design for 28nm SoC
Author :
Ho, Kevin ; Chou, Tsung-Yi ; Chen, Po-Kai ; Liou, David J.
Author_Institution :
Global Unichip Corp., Taiwan
Abstract :
As DDR DRAM is running at higher and higher speed, the shrinking data windows makes the timing closure in setup and hold at either DRAM or host chip more and more difficult. When calculating timing margins for DDR2/3 system, it helps to break up the uncertainty contributions into transmitter, interconnect and receiver categories. Furthermore, based on the timing margins, the signal integrity and power integrity analysis is the key point to reach success. We will also present our front-end experience of high-speed and low-power 28nm CPU core hardening, from top RTL integration to synthesis and DFT. This core includes dual-core ARM Cortex™-A9 CPU, Level 2 Cache Controller and Program Trace Macrocell.
Keywords :
DRAM chips; autoregressive moving average processes; cache storage; cellular arrays; high-speed techniques; integrated logic circuits; multiprocessing systems; receivers; system-on-chip; timing; transmitters; DDR DRAM; DFT; RTL integration; SoC; data windows; dual CPU core design; dual-core ARM CortexTM-A9 CPU; front-end experience; high-speed DDR2/3 PHY; high-speed low-power CPU core hardening; host chip; interconnect categories; level 2 cache controller; power integrity analysis; program trace macrocell; receiver categories; signal integrity; size 28 nm; timing margins; transmitter categories; Clocks; Computer architecture; Data models; Microprocessors; Stripline; System-on-a-chip; Timing;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2080-2
DOI :
10.1109/VLSI-DAT.2012.6212637
