Area and reliability efficient ECC scheme for 3D RAMs

Author

Chang, Li-Jung ; Huang, Yu-Jen ; Li, Jin-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

4

Abstract

Soft error is one critical issue faced by nano-scale random access memories (RAMs). Three-dimensional (3D) RAM with through-silicon via (TSV) is a new approach for overcoming the memory wall. A 3D RAM consists of multiple dies vertically stacked. Therefore, the upper die provides the shielding effect for the lower die. Thus, the SER in the upper die is higher than that in the lower die. This paper proposes an area and reliability efficient ECC (ARE-ECC) scheme for 3D RAMs by taking advantage of the shielding effect. An area and reliability optimization algorithm is also proposed to aid the designer to design the ARE-ECC scheme for 3D RAMs. Simulation results show that the ARE-ECC scheme can effectively increase the reliability of a 3D RAM using small area overhead.

Keywords

error correction codes; integrated circuit reliability; nanoelectronics; radiation hardening (electronics); random-access storage; shielding; three-dimensional integrated circuits; 3D RAM; ARE-ECC scheme; SER; TSV; lower die; memory wall; multiple dies; nano-scale random access memory; reliability efficient ECC scheme; reliability optimization algorithm; shielding effect; small area overhead; soft error; three-dimensional RAM; through-silicon via; upper die; Computer architecture; Error analysis; Error correction codes; Random access memory; Reliability engineering; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

PENDING

Print_ISBN

978-1-4577-2080-2

Type

conf

DOI

10.1109/VLSI-DAT.2012.6212645

Filename

6212645