A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines

A V-band low noise amplifier has been demonstrated in 90 nm CMOS. The LNA design was used the low loss microstrip lines for all matching networks. To fulfill the metal density requirement in fabrication, the ground plane needs slots. The direction of the slot pattern affects the line loss over 30% at 60 GHz, according to the analysis and experimental results. By slot filling under the line, the line loss can be improved 10% further. The topology of LNA is 3 stage common-source cascades for low supply voltage limited by process. Using the microstrip lines, the LNA exhibited a low noise figure of 5.6 dB and a gain of 10.8 dB at 60 GHz with only 5.5 mW from a 1.0 V power supply.