Design of a pipelined clos network with late release scheme

As the number of processor on a single chip grows, communication efficiency may dominate the performance of parallel programming. Achieving high throughput communication is a clear goal. In this paper, a novel 4-stage pipelined router is proposed for 3-stage Clos network and its corresponding network interface (NI). The proposed structure is built in DE3 and the performance is estimated using an in-house C++ simulator. To further improve the throughput, we propose a late release scheme (LRS) which reserves the allocated paths. The simulation result shows the throughput improvements are 9.42% and 42.91% under random and mixed traffic, respectively. The latency improvements are 5.1× and 2.53× under Jacobi linear equation simulation with 1k and 512 data sizes, respectively.