• DocumentCode
    2272730
  • Title

    Improving the First-Miss Computation in Set-Associative Instruction Caches

  • Author

    Ballabriga, Clement ; Casse, Hugues

  • Author_Institution
    Inst. de Rech. en Inf. de Toulouse, Univ. de Toulouse, Toulouse
  • fYear
    2008
  • fDate
    2-4 July 2008
  • Firstpage
    341
  • Lastpage
    350
  • Abstract
    The methods for worst case execution time (WCET) computation need to analyse both the control flow of the task, and the architecture effects involved by the hosting architecture. An important architectural effect that needs to be predicted is the instruction cache behavior. This prediction is commonly performed by assigning to each program instruction a category that describes its behavior. One of these categories, first miss, means that the first reference is a cache miss, while the subsequent references give hits. Yet, there is variations in the meanings of this category according to the used methods, capturing overlapping but not equivalents sets of cache behaviors. In this paper, we have analysed the shortcomings of the First-Miss computation methods, and we have deduced an improved first miss computation approach which captures a maximum of cache behaviors while eliminating some of the most time-consuming processing. We have implemented our method in the frame of C. Ferdinand´s categorization method, enhancing his approach for first miss handling, and compared it with the non-enhanced versions. The results shows a tighter WCET, and a greatly reduced computation time.
  • Keywords
    cache storage; cache behaviors; cache miss; first-miss computation; hosting architecture; instruction cache behavior; program instruction; set-associative instruction caches; time-consuming processing; worst case execution time computation; Computer aided instruction; Computer architecture; Control system analysis; Control systems; Hardware; Indium phosphide; Performance analysis; Real time systems; Turing machines; Uninterruptible power systems; WCET; abstract interpretation; instruction caches; static analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time Systems, 2008. ECRTS '08. Euromicro Conference on
  • Conference_Location
    Prague
  • ISSN
    1068-3070
  • Print_ISBN
    978-0-7695-3298-1
  • Type

    conf

  • DOI
    10.1109/ECRTS.2008.34
  • Filename
    4573129