Beyond VHDL: textual formalisms, visual techniques, or both?

Since a couple of years VHDL is the dominating hardware description language. There are very good reasons far this and simply the existence of VHDL as standardized language had a major impact on the advance of high level design techniques. In this paper some ideas about specification and modelling techniques beyond VHDL currently carried out in the author´s research group are discussed. One approach is to integrate formal specification techniques like evolving algebras (EA) and Z into a VHDL-oriented design environment. Other approaches concentrate on the potential of visual modelling techniques. Here techniques based on parallel logic programming like Pictorial Janus (PJ) or such ones based on higher order Petri Nets are under investigation