Title :
FPGA-specific optimizations by partial function evaluation
Author :
Manteuffel, Henning ; Bassoy, C.S. ; Mayer-Lindenberg, Friedrich
Author_Institution :
Inst. of Comput. Technol., Hamburg Univ. of Technol., Hamburg, Germany
Abstract :
Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.
Keywords :
circuit optimisation; field programmable gate arrays; high level synthesis; logic design; FPGA-specific optimization; compiler design; constant folding; data-width reduction; hardware-specific optimization; high-level synthesis; imperative program; memory access; memory intensive application; parallelization; partial function evaluation; Arrays; Clocks; Field programmable gate arrays; Indexes; Optimization; Runtime; Sections; FPGA; High-level synthesis; optimizations; partial evaluation;
Conference_Titel :
Electronic System Level Synthesis Conference (ESLsyn), 2011
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4577-0634-9
Electronic_ISBN :
978-1-4577-0632-5
DOI :
10.1109/ESLsyn.2011.5952283
