Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration

Author

Burgos, Rolando ; Chen, Zheng ; Boroyevich, Dushan ; Wang, Fred

Author_Institution

Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

fYear

2009

fDate

20-24 Sept. 2009

Firstpage

2293

Lastpage

2300

Abstract

This paper presents detailed design considerations of an ultra fast gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration using 0-Omega gate resistance. The proposed gate-drive achieved turn-on and turn-off times in the range of 12 to 55 ns operating from a 600 V dc bus with an inductive load of 10 A, and junction temperatures varying from 25deg to 200degC. An in-depth experimental evaluation is presented as well fully characterizing the performance attained by the proposed gate-drive circuit.

Keywords

driver circuits; junction gate field effect transistors; silicon compounds; wide band gap semiconductors; JFET; SiC; current 10 A; gate-drive circuit; inductive load; junction temperatures; phase-leg configuration; temperature 25 degC to 200 degC; time 12 ns to 55 ns; voltage 600 V; JFET; Schottky barrier diode (SBD); Silicon-Carbide (SiC); gate-drive circuit; phase-leg;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2893-9

Electronic_ISBN

978-1-4244-2893-9

Type

conf

DOI

10.1109/ECCE.2009.5316075

Filename

5316075