Title :
Improving device performance and variability for 28nm and beyond low power SoC technology using advanced implant solutions
Author :
Yang, C.L. ; Li, C.I. ; Lin, G.P. ; Tsai, C.H. ; Huang, Y.S. ; Fu, C. ; Lu, T.Y. ; Wang, H.Y. ; Chen, W.J. ; Chin, Y.L. ; Chan, M. ; Wu, J.Y. ; Chen, I.C. ; Colombeau, B. ; Guo, B.N. ; Wu, T. ; Gossmann, H. -J ; Lu, S.
Author_Institution :
Central R&D Div., United Microelectron. Corp., Tainan, Taiwan
Abstract :
Advanced junction scaling with device performance gain, leakage reduction and reduced threshold voltage (Vth) variation are critical for CMOS 28nm node and future scaling. In this paper, implant induced defect engineering for higher drive current with reduced SRAM defectivity, advanced junction formation and Vth mismatch (Vtmin) on a state-of-the-art 28nm logic flow are demonstrated and discussed.
Keywords :
CMOS integrated circuits; SRAM chips; system-on-chip; CMOS; SRAM defectivity reduction; Vth mismatch; Vth variation; Vtmin; advanced implant solutions; device performance improvement; higher drive current; leakage reduction; logic flow; low power SoC technology; size 28 nm; threshold voltage variation reduction; Abstracts; Implants; Junctions; Strain; Novel process technology; cryo implant; ion implantation; process modeling; strain relaxation;
Conference_Titel :
Junction Technology (IWJT), 2012 12th International Workshop on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4673-1258-5
Electronic_ISBN :
978-1-4673-1256-1
DOI :
10.1109/IWJT.2012.6212802
