Laser Thermal Annealing: Enabling ultra-low thermal budget processes for 3D junctions formation and devices

Annealing of 3D architectures is one of the major challenges for current and next generation devices for various applications ranging from sensors, microprocessors or high density memories. One of the most promising solutions is Laser Thermal Annealing (LTA), an ultrafast and low thermal budget process already adopted in production for passivation of BackSide Illuminated CMOS Imaging Sensors (CIS) and Power Diodes and Transistors (IGBT). The high temperature annealing required (>;1400°C) needs to be restrained to very thin layers while keeping low temperature of underlying fragile layers and devices. To achieve that, one needs to use a unique ultrafast annealing duration (sub μsec) and a proper Laser wavelength. This enables to reach metastable thermal processes, locking-in the electrical surface properties of the semiconductor while not damaging buried devices. We present a review of those new processes including recent development in emerging memory applications where 3D vertical stack of functional layers of devices is realized.