Using edge-triggering in the asynchronous synthesis of write-after-read operations

This paper introduces enhancements to the synthesis of circuits that involve write-after-read (WAR) operations and use the four-phase handshake protocol. The paper demonstrates that the use of edge-triggering makes possible many useful trade-offs among speed, area and power-delay product. Significant increases in speed are possible as a result of increased concurrency in the circuitpsilas operation, which compensates for much of the penalty associated with the down phase of the four-phase protocol. Simulation results for a 16-bit accumulator showed a speed increase of 50% and a reduction of 23% in the power-delay product. As an example of a larger circuit, the speed of a radix-4 Booth multiplier increased by over 27% and its area and energy consumption were reduced by 5%. Test circuits were synthesized using Balsa and implemented in Synopsys using 180-nm technology.