A new chaotic key-based design for image encryption and decryption

Author

Jui-Cheng ; Guo, Jim-In

Author_Institution

Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Taiwan, China

Volume

4

fYear

2000

fDate

2000

Firstpage

49

Abstract

In this paper, an image encryption/decryption algorithm and its VLSI architecture are proposed. According to a chaotic binary sequence, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. Its features are as follows: (1) low computational complexity, (2) high security, and (3) no distortion. In order to implement the algorithm, its VLSI architecture with low hardware cost, high computing speed, and high hardware utilization efficiency is also designed. Moreover, the architecture of integrating the scheme with MPEG2 is proposed. Finally, simulation results are included to demonstrate its effectiveness

Keywords

VLSI; binary sequences; chaos; computational complexity; cryptography; image coding; MPEG2; VLSI architecture; chaotic binary sequence; chaotic key-based design; computational complexity; computing speed; gray level; hardware cost; hardware utilization efficiency; image decryption; image encryption; security; Algorithm design and analysis; Binary sequences; Chaos; Computational complexity; Computer architecture; Costs; Cryptography; Hardware; Security; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858685

Filename

858685