DocumentCode
2274961
Title
Microarchitecture of HaL´s CPU
Author
Patkar, N. ; Katsuno, A. ; Li, S. ; Maruyama, T. ; Savkar, S. ; Simone, M. ; Shen, G. ; Swami, R. ; Tovey, D.
Author_Institution
HaL Comput. Syst., Campbell, CA, USA
fYear
1995
fDate
5-9 March 1995
Firstpage
259
Lastpage
266
Abstract
The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.
Keywords
instruction sets; multiprocessing systems; parallel architectures; 64 bit; 64-bit SPARC Version 9 instruction set architecture; Hat PM1 CPU; dataflow model; register renaming; superscalar instruction issue; Availability; Central Processing Unit; Computer aided instruction; Computer architecture; Maintenance; Microarchitecture; Out of order; Pipelines; Registers; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon '95.'Technologies for the Information Superhighway', Digest of Papers.
Conference_Location
San Francisco, CA, USA
ISSN
1063-6390
Print_ISBN
0-8186-7029-0
Type
conf
DOI
10.1109/CMPCON.1995.512394
Filename
512394
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