DocumentCode
2274980
Title
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
Author
Hamada, Naohiro ; Shiga, Yuuki ; Saito, Hiroshi ; Yoneda, Tomohiro ; Myers, Chris ; Nanya, Takashi
Author_Institution
Aizu Univ., Aizuwakamatsu
fYear
2008
fDate
23-27 June 2008
Firstpage
50
Lastpage
55
Abstract
This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.
Keywords
C language; asynchronous circuits; circuit analysis computing; network synthesis; C language; RTL model; asynchronous circuits; behavioral description; behavioral synthesis method; bundled-data implementation; Asynchronous circuits; Circuit synthesis; Clocks; Control system synthesis; Informatics; Processor scheduling; Resource management; Scheduling algorithm; Signal synthesis; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on
Conference_Location
Xian
ISSN
1550-4808
Print_ISBN
978-1-4244-1838-1
Electronic_ISBN
1550-4808
Type
conf
DOI
10.1109/ACSD.2008.4574595
Filename
4574595
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