• DocumentCode
    2275012
  • Title

    HGA: A Hardware-Based Genetic Algorithm

  • Author

    Scott, Stephen D. ; Samal, Ashok ; Seth, Sharad

  • Author_Institution
    Washington University, St. Louis, MO
  • fYear
    1995
  • fDate
    1995
  • Firstpage
    53
  • Lastpage
    59
  • Abstract
    A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware´s speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2-3 orders of magnitude faster than the software-based GA.
  • Keywords
    Field Programmable Gate Arrays (FPGAs); Function Optimization; Parallel Genetic Algorithms; Performance Acceleration; Performance Evaluation; Coprocessors; Design optimization; Engines; Field programmable gate arrays; Genetic algorithms; Hardware; Problem-solving; Robustness; Scalability; Software prototyping; Field Programmable Gate Arrays (FPGAs); Function Optimization; Parallel Genetic Algorithms; Performance Acceleration; Performance Evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Gate Arrays, 1995. FPGA '95. Proceedings of the Third International ACM Symposium on
  • Print_ISBN
    0-7695-2550-4
  • Type

    conf

  • DOI
    10.1109/FPGA.1995.241945
  • Filename
    1377261