An accurate statistical yield model for CMOS current-steering D/A converters

Author

van den Bosch, A. ; Steyaert, M. ; Sansen, Willy

Author_Institution

Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee

Volume

4

fYear

2000

fDate

2000

Firstpage

105

Abstract

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time

Keywords

CMOS integrated circuits; digital-analogue conversion; impedance matching; integrated circuit modelling; integrated circuit yield; probability; statistical analysis; CMOS current-steering DAC; D/A converters; INL yield; current source transistors; digital-to-analog converter; high resolution DAC; integral nonlinearity; matching behavior; statistical yield model; CMOS digital integrated circuits; CMOS technology; Central Processing Unit; Digital-analog conversion; GSM; HDTV; Semiconductor device modeling; Signal design; Silicon; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858699

Filename

858699