DocumentCode :
2275183
Title :
A methodology for MOS transistor mismatch parameter extraction and mismatch simulation
Author :
Serrano-Gotarredona, T. ; Linares-Barranco, B.
Author_Institution :
Nat. Microelectron. Center, Spain
Volume :
4
fYear :
2000
fDate :
2000
Firstpage :
109
Abstract :
This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical simulators, like HSpice. A measurement and extraction procedure has been carefully designed to be able to obtain reliable measurements of the mismatch parameters of a given technology. The correctness of this extraction procedure method has been checked through three different validation methods. We also present two methods for performing mismatch simulation with conventional circuit simulators (like HSpice) using the extracted parameters
Keywords :
CMOS analogue integrated circuits; MOSFET; SPICE; VLSI; circuit simulation; impedance matching; integrated circuit design; HSpice; MOS transistor; circuit simulators; electrical simulators; mismatch parameter extraction; mismatch simulation; validation methods; Circuit simulation; Curve fitting; Data mining; MOSFETs; Microelectronics; Parameter extraction; Semiconductor device measurement; Very large scale integration; Virtual manufacturing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
Type :
conf
DOI :
10.1109/ISCAS.2000.858700
Filename :
858700
Link To Document :
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