Simulation study of junctionless vertical MOSFETs for analog applications

In this paper, we use the junctionless (JL) technology to design both JL middle-gate vertical MOS (JLMGVMOS) and JL pseudo tri-gate VMOS (JLPTGVMOS) for performance comparison on analog metrics. According to TCAD simulations, the JLPTGVMOS devices demonstrate excellent characteristics, such as high transconductance (g_m), transconductance generation factor (g_m/I_d), and voltage gain A_vi, when compared with the JLMGVMOS devices. This is owing to its better gate controllability over the channel charges. Although a larger drain conductance g_d, resulting in a smaller drain output resistance r_o, is observed for JLPTGVMOS devices compared with JLMGVMOS devices, these results are still within acceptable limits. Additionally, we also find out that the impacts of gate material (n+ poly-Si or p+ poly-Si) on the analog properties merely result in a large threshold voltage shift.