Analysis of different protocol description styles in VHDL for high-level synthesis

When synthesizing control-flow dominated descriptions based on VHDL, different styles of semantically equivalent descriptions may differ significantly in quality. This paper discusses the effect of the input description on High-Level Synthesis when using VBDL. In order to show this effect, a high speed protocol based on the ISO reference protocol Abracadabra is used. Five VHDL descriptions styles of the same protocol have been synthesized using AMICAL, a VHDL based behavioral synthesis tool. Discussions of the different results leads to a VHDL based methodology for protocol modelling in order to produce efficient designs