DocumentCode :
2275692
Title :
Using selective voltage binning to maximize yield
Author :
Lichtensteiger, Susan ; Bickford, Jeanne
Author_Institution :
IBM Corp. Syst. & Technol. Group, Essex Junction, VT, USA
fYear :
2012
fDate :
15-17 May 2012
Firstpage :
7
Lastpage :
10
Abstract :
Yield loss associated with leakage screens is increasing as products migrate to technologies with thinner gate oxide and more aggressive lithography. Product competitiveness requires meeting low power and when products have exhausted design options, tighter than 3 sigma fast leakage screens are implemented to reduce power which can result in significant yield loss. Selective Voltage Binning (SVB) provides a way to interlock a lower operating voltage in the system with process window information so that faster parts can be run in the system at a lower voltage avoiding the yield loss associated with custom leakage screens.
Keywords :
integrated circuit design; integrated circuit testing; integrated circuit yield; 3 sigma fast leakage screens; aggressive lithography; leakage screens is; process window information; product competitiveness; selective voltage binning; yield loss; yield maximization; Capacitance; Manufacturing; Patents; Performance evaluation; Power system dynamics; Semiconductor device measurement; Timing; IDDQ; leakage; screen; voltage binning; yeild;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2012 23rd Annual SEMI
Conference_Location :
Saratoga Springs, NY
ISSN :
1078-8743
Print_ISBN :
978-1-4673-0350-7
Type :
conf
DOI :
10.1109/ASMC.2012.6212859
Filename :
6212859
Link To Document :
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