• DocumentCode
    2275754
  • Title

    Optimizing product yield using manufacturing defect weights

  • Author

    Bickford, Jeanne Paulette ; Hibbeler, Jason D. ; Mueller, Dirk ; Peyer, Sven ; Kumar, Vasanth S.

  • Author_Institution
    IBM Corp. Syst. & Technol. Group, Essex Junction, VT, USA
  • fYear
    2012
  • fDate
    15-17 May 2012
  • Firstpage
    16
  • Lastpage
    20
  • Abstract
    Yield of 45nm products can be optimized by adjusting how the router is run. While forcing wiring to upper levels adds wire length and increases the number of vias, sensitivity to random defects is reduced. Wire spreading does not improve yield for 45nm products.
  • Keywords
    integrated circuit yield; network routing; wires (electric); wiring; manufacturing defect weight; product yield optimization; router; size 45 nm; wiring; Metals; Optimization; Product design; Routing; Sensitivity; Wires; Wiring; Design for Manufacturing (DfM); Manufacturability; Routing; Yield;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference (ASMC), 2012 23rd Annual SEMI
  • Conference_Location
    Saratoga Springs, NY
  • ISSN
    1078-8743
  • Print_ISBN
    978-1-4673-0350-7
  • Type

    conf

  • DOI
    10.1109/ASMC.2012.6212861
  • Filename
    6212861
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2275754