Modeling ASIC memories in VHDL

Author

Balaji, Ekambaram ; Krishnamurthy, P.

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

1996

fDate

16-20 Sep 1996

Firstpage

502

Lastpage

508

Abstract

Memories are all important component in ASIC designs. With increasing design complexities, there is need to model memory devices with a high level of accuracy and simulation efficiency. This paper describes the functional/timing aspects of VHDL memory models, their implementation, and various issues involved. The paper also presents a generic interface package used in the development of memory models

Keywords

SRAM chips; application specific integrated circuits; circuit analysis computing; flip-flops; hardware description languages; integrated circuit design; integrated circuit modelling; logic CAD; memory architecture; read-only storage; timing; ASIC designs; ASIC memories; ROM; VHDL memory models; functional aspects; generic interface package; simulation efficiency; static RAM; timing aspects; Application specific integrated circuits; Clocks; Design engineering; Electrooptic devices; Flip-flops; Hardware design languages; Large scale integration; Memory architecture; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European

Conference_Location

Geneva

Print_ISBN

0-8186-7573-X

Type

conf

DOI

10.1109/EURDAC.1996.558250

Filename

558250

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2275942