Standardizing delay calculation in Verilog

Verilog HDL and PLI provide all the necessary means for accurate delay modeling and calculation. However, appropriate use of a delay calculator is often problematic due to the multitude of libraries and delay models used in a single design and the lack of explicit standards in delay specifications. This paper is intended to set a standard, not to provide a new in-depth method. The basic delay models used for calculating the design specific delays are reviewed and the common parameters used by all library vendors are identified. It is shown that the process of characterizing cells for certain generally accepted common delay parameters can be independent of the individual delay calculation algorithms and/or the required accuracy of the delay calculation process