Title :
Verilog-based performance evaluation of a multiprocessor system
Author :
Anyanwu, C.D. ; Jalowiecki, I.P.
Author_Institution :
Brunel Univ., Uxbridge, UK
Abstract :
We present the outcome of an exercise to model, in Verilog HDL, a non-homogeneous, pyramid-organised, multiprocessor system. The model has been constructed to represent, at varying degrees of detail, the dynamic behaviour of the system and has subsequently been verified and calibrated against components of the realised system. The paper discusses the performance of the model, the type of results available, and the experience gained from the activity
Keywords :
hardware description languages; multiprocessing systems; performance evaluation; ASTRA; Verilog-based performance evaluation; dynamic behaviour; nonhomogeneous pyramid-organised multiprocessor system; Analytical models; Application specific processors; Computer buffers; Computer performance; Hardware design languages; Los Angeles Council; Multiprocessing systems; Performance analysis; Procurement; System analysis and design;
Conference_Titel :
Verilog HDL Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-7082-7
DOI :
10.1109/IVC.1995.512471
