The analysis of device performance on a different shallow trench isolation (STI) liner scheme

The space of STI is considered as critical parameter for filling the STI trench free of void. On the other hand, as thickness of liner is thinner, it is insufficient to trap mobile charge and to satisfy the adhesion. The impact of STI liner with mechanical stress on electrical performance was studied. The performance increase from changing the liner scheme was verified 3%, 8% in narrow width transistor respectively. The stress effect due to changing the liner scheme showed the more sensitive to PMOS rather than NMOS. Using the thinner liner oxidation make the performance increase considering the stress effect. A kind of the material being used among gap filling in the STI trench is considered on mechanical stress effect, since this affects the slight better or worse behavior on the device performance on CMOS technology.