Leakage power characterization and minimization in 3D stacked multi-core chips with microfluidic cooling

The needs of multiple-functionality and low cost have driven the development of high-density electronic packages. However, the greater package density results in higher power density per unit volume of the package, which creates challenges for thermal management. Microfluidic cooling can potentially achieve superior thermal performance with surface area enhancements such as pin fins and could be a viable solution for many applications to the increasing power density in electronic packages. In this paper, we report on investigations of the impact of the microfluidic cooling technology on the system level performance of multicore architectures stacked in a 3D package. Specifically, we characterize the impact on leakage power dissipation over different pin fin configurations and its impact on overall system energy efficiency. We do so with a cycle-level application-driven full system simulation framework. The framework executes application binaries and operating system code and models coupled interactions among the i) application & operating system code, ii) resulting thermal field, iii) leakage power, and v) microfluidic cooling. This provides the unique ability to assess the impact of microfluidics on computing system level metrics experienced by the applications such as energy per instruction. We illustrate and quantify improvements in energy efficiency of the applications, as well as increase in throughput due to microfluidic cooling.