Towards maximising the use of structural VHDL for synthesis

In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that: design, debug and simulation times are reduced; designs are more accessible (readable, modifiable, portable, reusable); design prototyping can be speeded up. All of this can be achieved without the need to modify existing synthesis tools