A Verilog preprocessor for representing datapath components

Describes research leading to the generation of a preprocessor for the Verilog hardware description language. The function of this preprocessor is to support repeated feature instances in a Verilog description for a digital system. Repeated features most commonly occur in the description of datapaths, where iterative structures like adders, multipliers and muxes are the basic building blocks. Citations from Verilog users and industry organizations in support of inclusion of a repeated feature syntax are given. Several syntaxes for describing repeated features are presented. From these proposals, a single syntax for support of repeated feature instances is selected. A preprocessor is described that will parse the extended Verilog and translate it to supported Verilog. The challenges in the generation of the preprocessor are given. The paper concludes with a status report on the preprocessor and thoughts for future development