Title :
A virtual memory management scheme for simulation environment
Author :
Mittra, Swapnajit
Author_Institution :
WIPRO Infotech Inc., USA
Abstract :
A virtual memory management scheme is proposed for integrating large memory in the simulation environment. This is a novel extension to the Verilog-XL simulator from Cadence Design Systems. The scheme provides a user-transparent mechanism to instantiate a large chunk of memory without being limited by the main-memory of the simulating machine
Keywords :
Computational modeling; Computer simulation; Environmental management; Hardware design languages; Hydrogen; Memory management; Modems; Predictive models; Programming profession; Virtual prototyping;
Conference_Titel :
Verilog HDL Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-7082-7
DOI :
10.1109/IVC.1995.512505
