A comprehensive pre-RTL IC design methodology

Complex integrated circuit (IC) designers must make design decisions to meet the functional and performance requirements of their specific ICs prior to register-transfer level (RTL) coding. CMEG, a comprehensive pre-RTL IC design methodology, is described. It is illustrated through an example of an image processing algorithm, and is compared against hardware description language and behavioral synthesis design methods. CMEG consists of the following steps: C_apture behavior graphically, M_ap operations to hardware instances, E_valuate designs graphically via simulation, and G_enerate RTL models and validation vectors automatically. This comprehensive methodology offers the following benefits: (1) CMEG is pragmatic. (2) CMEG is useful for a wide range of application domains and IC design styles. (3) CMEG provides developers with total control. (4) CMEG allows developers to validate functionality and architecture prior to RTL construction. (5) CMEG produces better IC designs in less time. Using this methodology, designers need only work at the architectural level. At this level, the RTL model, correct by construction, is automatically derived from the architectural model, and all the logic expressions are automatically generated and correct by construction. Validating design graphically at a higher level of design abstraction improves designer confidence in the RTL model. CMEG gives developers added flexibility to maintain and enhance their designs and to establish better communication with other designers, as well as with managers and customers