DocumentCode
2276957
Title
Perception-aware H.264/AVC encoder with hardware perception analysis engine
Author
Wu, Guan-Lin ; Wu, Tung-Hsing ; Fu, Yu-Jie ; Chien, Shao-Yi
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2010
fDate
19-23 July 2010
Firstpage
790
Lastpage
795
Abstract
In order to increase coding efficiency, a perception-aware H.264/AVC encoder is proposed in this paper. With a different perception models for intra-frames and inter-frames, the initial quantization parameter (QP) is perceptually adjusted to remove perceptual redundancy. Moreover, the associated hardware architectures of the whole encoder and the perception analysis engine are also proposed with hardware sharing and pipelining design techniques. Experimental results show that our encoder achieves about 6-27% bit-rate saving in the QP range of 28-36. Furthermore, the hardware cost of the perception analysis engine is 120K gates, which is acceptable to be integrated into an H.264/AVC encoder chip.
Keywords
data compression; digital signal processing chips; quantisation (signal); video coding; H.264/AVC encoder chip; hardware architectures; hardware perception analysis engine; hardware sharing; perception aware H.264/AVC encoder; pipelining design techniques; quantization parameter; Encoding; Engines; Hardware; Image color analysis; PSNR; Pixel; Streaming media; H.264/AVC; Just Noticeable Distortion; Perception-aware coding; Perceptual coding; SSIM;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo (ICME), 2010 IEEE International Conference on
Conference_Location
Suntec City
ISSN
1945-7871
Print_ISBN
978-1-4244-7491-2
Type
conf
DOI
10.1109/ICME.2010.5582545
Filename
5582545
Link To Document