A ultra high speed clock distribution technique using a cellular oscillator network

This paper describes a novel process-gradient insensitive GHz clock distribution technique using a Cellular Oscillator Network. With its inherent structural synchronous characteristics, the Cellular Oscillator Network can be used in microprocessors or high-speed digital logic, where ultra high speed clock distribution with picosecond order clock skew is inevitably needed. A sleeping mode technique is also presented for power minimization. This new technique is simulated and proved with typical 3 V, 0.8 μm CMOS N-well process parameters