An extendible MIPS-I processor kernel in VHDL for hardware/software co-design

This paper discusses the design of a MIPS-I processor kernel using VHDL. The control structure of this processor is distributed with a small controller in each pipeline stage controlling sequencing of operations and communication with adjacent pipeline stages. Instruction flow management is performed using asynchronous communication signals. Due to its high-level description and distributed control structure, the kernel can easily be extended. Thus, instruction set extension hardware/software co-evaluation can be performed efficiently using rapid prototyping