Analysis of flow and heat distribution in a 3D stack of chips and memories with back side two-phase cooling

Three-dimensional integration of multiple stacked silicon dies using Through-Silicon Vias has been recognized as a likely future direction of integrated circuit design. Yet, in contrast to previous architectures such 3D-ICs require extensive attention to thermal management from the moment of conception. Although such stacks are often associated with integrated, interlayer cooling solutions, it is conceivable that a single microchannel evaporator might provide a simpler cooling solution to support a stack of modest size, especially if made from dies of 50-μm thickness, that are now feasible to manufacture. The current study explores such a solution for a stack of 6 layers, focusing on the interaction of hot spot placement among the layers with the two-phase cooling and flow distribution among the channels of the micro-evaporator. The simulation code is based on numerous methods proven experimentally to work well for the present small size of channels and fluid. The study suggests that such configurations are feasible, yet require careful consideration of the effect of hot spot placement to yield good micro-evaporator performance and safe cooling of the electrical components.