Design rules for post-CMOS through silicon vias in an industrial environment

Through-silicon via technology is becoming inevitable to follow the increasing interconnect density required in today´s logic products. But there are advantages to other markets as well: system-in-package solutions that integrate MEMS and ASIC chips have clearly different requirements, i.e. increased robustness against mechanical stress. Rather than targeting for ultra-thin silicon, they require standard wafer thicknesses. This article lines out some challenges in the implementation of a viable post-CMOS feedthrough technology in this domain.